Senior Imager Device Engineer
- Site: Boise, Idaho
Aptina Imaging is a division of Micron Technology. As a Senior Device Engineer at Aptina in San Jose, California, you will be responsible for determining device targets and providing the device development, analysis, characterization, reliability, and marginality study for Aptina's next-generation CMOS imager technology. Using design of experiments and statistical data analysis methods, coupled with your ability to efficiently evaluate physical and electrical data, you will understand any process impacts and optimize device performance and reliability.
In this position, you will work and interface with a wide variety of people and groups in different areas of Research and Development (R&D) and Manufacturing. In addition to working with the Device Simulation Group on device modeling, you will be working with the Process Integration, Product, and Design groups to determine the process flow and the electrical and layout design rules, as well as to analyze and debug device and circuit-related issues during process development. You will also work closely with the Layout and Parametric groups to determine scribe test structure layout, parametric program setup, and bench measurements based on the electrical characterization requirements. With the Spice Modeling Group, you will define device spice models and process parametric targets, including spice model targets and model box limits, and coordinate the definition of device modeling test structures. You can also expect to work with the Device Reliability Group, as well as the ESD and Latch-up Group in defining ESD and latch-up test structures and characterization. You will also provide device engineering support to the production Fab on product characterization and qualification.
Successful candidates for this position will have:
- At least five years of experience in semiconductor device engineering.
- The ability to work with and interface with a wide variety of people and groups in different areas of R&D and Manufacturing.
- A highly motivated, goal-oriented personality.
- The ability to aggressively execute complex experiments and focus on solving problems individually or as part of a team.
- The ability to accomplish tasks in a timely manner.
- Excellent verbal and written communication skills.
- Experience with data analysis software such as JMP, RS1, and Excel.
- A thorough knowledge of CMOS device physics, state-of-the-art CMOS process technologies, and process integration.
- Familiarity with TCAD tools for process and device simulation (preferred).
- Device development experience on 90nm and newer logic technologies (preferred).
- Familiarity with Cadence for test structure layout verification (preferred).
- Proficiency in semiconductor device measurement techniques (preferred).
Education:
MS or PhD in Electrical Engineering, Physics, or a related field is required.
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