CAD Engineer
- Site: San Jose
Aptina Imaging is a division of Micron Technology. As an Imager CAD Engineer at Aptina in San Jose, California, you will be responsible for supporting Design Engineering by writing and maintaining software utilities and tools. In this position, you will define, implement, automate, test, and support physical design verification methodologies for CMOS Imaging IC designs. You will be tasked with creating and maintaining IO/ESD/latchup verification flow. Additionally, you will be an intricate part of a CAD design team developing and integrating tools into a design flow in order to satisfy R&D verification requirements. This position also requires that you specialize in Design Rule Check (DRC); Layout verses Schematic (LVS) and schematic Electrical Rule Checking (ERC). You will also be involved in evaluating Design Automation tools, and developing new tools using PERL and SKILL programming languages. Other duties include supporting Design Automation and in-house tools, designing programs and flows to integrate new tools, and evaluating customer needs.
Successful candidates for this position will have:
- General knowledge of the CMOS semiconductor process.
- Experience with an EDA framework and Cadence DF2 experience.
- A strong programming background using PERL or Tk_Tcl (preferred).
- Familiarity with Physical Verification tools (DRC, LVS, and LPE).
- Knowledge of Synopsys Hercules tools as well as Mentor Graphics Calibre tools.
Education:
BS in Electrical Engineering, Physics, Computer Engineering
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